The present invention relates to a method for synchronizing an isochronous system with a previously independent topologically higher-ranking clock pulse system. For differentiation from the higher-ranking clock pulse system, the clock pulse system of the isochronous system, which is to be connected to the higher-ranking clock pulse system, is referred to in the following as an isochronous basic clock pulse system or in short as a basic clock pulse system.
The following discussion of related art is provided to assist the reader in understanding the advantages of the invention, and is not to be construed as an admission that this related art is prior art to this invention.
An example of a basic clock pulse system can include a plurality of fundamentally independent components or devices—in the following referred to collectively as components—is a system in the form of a production machine, a machine tool, a robot or the like. In the following, a system of this kind is referred to collectively, but without sacrificing broader generality, as a production machine.
In a basic clock pulse system of this kind, it is known to use a plurality of clock pulses with different periods, which, on the one hand, all have to be synchronized between the components of the basic clock pulse system and, on the other, must also be in a defined phase relationship to one another.
This requires the following consistency conditions to be fulfilled:                a component functioning as a master clock issues a clock pulse, which is hereinafter referred to as a communication clock pulse, to the other components of the basic clock pulse system. The period of the communication clock pulse determines the shortest clock pulse that can be used in the basic clock pulse system. All components are synchronized with the communication clock pulse by means of a local clock pulse generator, in particular a local, digital PLL (DPLL), and the start of the clock pulse period of each other clock pulse in the basic clock pulse system always coincides with the start of a period of the communication clock pulse.        in addition to the communication clock pulse, the master clock generates a special system clock pulse with which the start of each clock pulse period coincides with the start of the clock pulse periods of all the other inter-synchronized clock pulses. The period of a clock pulse of this kind is the lowest common multiple of the periods of all other clock pulses of the basic clock pulse system. Correspondingly, this is referred to as an LCM clock pulse (LCM=lowest common multiple).        
On the basis of the communication clock pulse output by the master clock, each component in the basic clock pulse system generates an independent clock pulse system, which, with the aid of a local clock pulse generator (local DPLL) and other suitable measures fulfils the consistency conditions with respect to the clock pulse system of the master clock. In this case, each consistency condition already achieved is maintained for each component in the basic clock pulse system—partially with the aid of a DPLL.
To connect an isochronous basic clock pulse system of this kind to a previously independent topologically higher-ranking clock pulse system, all clock pulses of the basic clock pulse system have to be phase-shifted so that the two systems are combined to form an overall isochronous system. Here, the phase shift has to take place such that, on the one hand, the consistency of the clock pulses in relation to each other and beyond the different components of the basic clock pulse system is at no time inadmissibly disrupted and that, on the other hand, after the phase shift, the clock pulse systems can be combined such that the consistency conditions mentioned also apply to the overall system.
To date, it has been provided with a method for synchronizing an isochronous system with a higher-ranking clock pulse system that the consistency conditions for all local clock pulses within a component are set and checked by means of a software routine. Here, hardware counters are used to check the phase position of the clock pulses and it is possible to program a phase shift which is then executed in hardware. This only succeeds if the hardware counters for the different clock pulses are read out consistently, i.e. if it is ensured that all counters can be read out before a counter content changes. In a real-time system, this means that this software routine has to be assigned to the quickest time slot.
Between different components, the consistency conditions can only be fulfilled by observing the communication taking place at previously defined times with telegrams defined by a respective protocol. For selective synchronization, the instant of time at which the aforementioned software routine runs is aligned not only with the internal counters but also with the communication. In order to avoid this additional restriction, the phases of the clock pulses affected are changed not selectively, but successively until a faultless communication enables it to be identified that the consistency condition has been fulfilled.
In the case of connection to a higher-ranking clock pulse system, the master clock of the basic clock pulse system first informs all components of the basic clock pulse system that a phase shift is taking place. With the previous method, the master clock then shifts its own clock pulse system until it is synchronous with the higher-ranking clock pulse system. During this, the master clock uses a constant step size for each communication clock pulse. Finally, the master clock informs the other components of the basic clock pulse system that the phase shift has been completed.
This achieves synchronicity of the master clock of the basic clock pulse system with the higher-ranking clock pulse system. During this adaptation and following the adaptation, the master clock continuously emits the communication clock pulse that is authoritative for all components of the basic clock pulse system.
However, the DPLL, with which the other components are held in synchronism with the master clock, is generally optimized in order to suppress interference noise (jitter). This means it is not able to follow the step size during the phase shift (see FIG. 5). Therefore, for a temporary period, another synchronization method is used, which, although it can follow the phase shift, is not able to suppress the jitter. With this other synchronization method, there is an abrupt adaptation of the clock pulse period.
The drawback with this known method for synchronizing an isochronous basic clock pulse system with a previously independent topologically higher-ranking clock pulse system is that, due to the abrupt change to the clock pulse period, in addition to the residual jitter, faultless communication with the master clock is no longer guaranteed, for example due to a violation of one of the transmit time slots assigned to the component. One consequence of communication that is no longer faultless is, for example, that the production machine is automatically brought to a stop.
It would therefore be desirable and advantageous to obviate prior art shortcomings and to provide an improved method for synchronizing an isochronous basic clock pulse system with a previously independent topologically higher-ranking clock pulse system with which the above-described drawbacks are avoided or at least the impacts thereof are reduced.